1. Field of the Invention
The present invention relates generally to semiconductor wafer fabrication, and more particularly to a method for planarizing insulating and other layers formed over such substrates.
Planarization of semiconductor substrate surfaces during fabrication of fine-geometry integrated circuits is necessary to improve both photolithographic feature resolution and dimensional control, and to alleviate metallization discontinuity which may result from abrupt changes in topography.
Two commonly employed methods for planarization involve the deposition of a sacrificial leveling layer, such as a photoresist, to fill the voids and crevices which are present following application of an insulating layer. The flat surface created by the combined sacrificial and insulating layers is etched back at a uniform rate to leave a generally flat layer of insulating material having a desired thickness. The first of these methods employs ion beam erosion of the sacrificial and insulating layers which, although workable, is a relatively slow technique capable of removing only about 1000 .ANG. per minute. The second technique utilizes conventional high frequency, low pressure plasma etching for removing the sacrificial layer. While such plasma etching is somewhat more rapid than ion beam erosion, it still takes a long time to etch relatively thick planarization layers, which may have thicknesses in the range from 2 to 5 .mu.m.
Such thick planarization layers are required in order to adequately cover underlying irregularities and provide for a level surface from which to start the etch back process. The planarization materials, which are typically applied by spin-on techniques, are relatively viscous and will propagate the underlying surface topology, at least in part. This is particularly true when relatively thin layers are utilized, which tend to spread much more thinly over relatively narrow features than over relatively wide features. Thus, in order to enhance the planarity of the planarization layers, relatively thick layers have been utilized in the past.
For the above reasons, it would be desirable to provide improved methods for planarizing substrate surfaces, particularly to provide for improved techniques for applying relatively thin planarization layers which display enhanced surface planarity. The use of relatively thin planarization layers decreases the processing time required for etching back such layers, and the enhanced planarity improves both photolithographic feature resolution and dimensional control, and decreases the likelihood of metallization discontinuities which may result from lack of planarity.
2. Description of the Background Art
Planarization techniques employing ion beam erosion of sacrificial and insulating layers are described in Johnson et al. (1982) Appl. Phy. Lett. 40:636; Johnson et al. (1983) J. Vac. Sci. Technol. B1:487; and Mogami et al. (1985) J. Vac. Sci. Technol. B3:857. Methods for planarization using a plasma etch of a sacrificial layer are described in Adams and Capio (1981) J. Electrochem. Soc. 128:423. See also, U.S. Pat. Nos. 4,358,356 and 4,377,438 which discuss alternate planarization techniques.